1. Field of the Invention
The present invention relates to a control circuit, and more particularly, to a power-saving control circuit including a first-in first-out (FIFO) register.
2. Description of Related Art
With the coming of the digital era and the trend for marketing hot multimedia and digital products, consumers have increasing demands on computer specifications. Anything from the speed of circuit operation to the power-saving features and the powering capacity of a battery have become major considerations. However, the price to be paid for increasing the operating speed is often the consumption of more power. As a result, power-saving devices in circuits have become increasingly important. Nowadays, more attention is paid on the development of power-saving devices.
When data is transmitted between interfaces having a different operating speed, a structure including a first-in-first-out (FIFO) register is often used. The hand shaking of data with the FIFO register is mostly achieved through the communication of pointers so that whether the FIFO register contains any data can be determined before data is transmitted or received. More specifically, the FIFO register receives the data from a transmitting end in high speed, stores the data in a memory and waits for a receiving end to read out the data. When the receiving end is free, the receiving end reads out the data in the order which the data is previously stored.
FIG. 1(a) through (e) are diagrams of conventional system structures that use the FIFO register to transmit data. First, as shown in FIG. 1(a), the first circuit module 110 and the second circuit module 120 are modules having different transmission speeds. Data in the first circuit module 110 is transmitted to the second circuit module 120 through the FIFO register 130. Here, a FIFO register 130 with only four record locations is used as an example so that the data transmission process can be explained more easily.
The first circuit module 110 relies on the write pointer (WPTR) to determine which of the record locations of the FIFO register 130 the data is written to. The second circuit module 120 determines to read the data from which of the record locations of the FIFO register 130 through the read pointer (RPTR). When the first circuit module 110 writes data into the FIFO register 130, a write pointer (WPRT) is simultaneously transmitted to the second circuit module 120 so that the second circuit module 120 may know the location where the data is written. When the write pointer and the read pointer are matched, this implies that the FIFO register contains no more data and the second circuit module 120 stops working. On the other hand, when the write pointer is not equal to the read pointer, this implies that the FIFO register still contains unread data and so the second circuit module 120 reads out the data.
For example, assume that both the write pointer and the read pointer point to the zeroth record location of the FIFO register 130 in the beginning as shown in FIG. 1(a). When the first circuit module 110 needs to write data, the data is written to the location pointed to by the write pointer, that is, the zeroth record location. After the data is written in, the write pointer is directed to the next record location sequentially, that is, the first record location as shown in FIG. 1(b). Meanwhile, the foregoing write pointer is also transmitted to the second circuit module 120. The second circuit module 120 will discover that the record location pointed to by the write pointer is not the same as the record location pointed to by the read pointer. Therefore, the data in the zeroth record location is read out and then the read pointer is renewed to point to the first record location as shown in FIG. 1(c). Because the record location pointed to by the read pointer and the write pointer is the same, reading is stopped.
Next, if new data arrives, the data is written to the first record location. After the data is written in, the write pointer automatically points to the second record location as shown in FIG. 1(d). Similarly, the second circuit module 120 will discover that the record location pointed to by the write pointer is not the same as the record location pointed to by the read pointer. Therefore, the data in the first record location is read out and then the read pointer is renewed to point to the second record location as shown in FIG. 1(e). In a similar way, when other data arrives, the foregoing steps are repeatedly executed to transmit data between interfaces having different operating speeds.
However, in the conventional technique, the power saving for operating the FIFO register is not considered. When the first circuit module 110 is linked to the second circuit module 120 to transmit data, the clock signal of the circuit is turned on at all times. Yet, even in the absence of data transmission, the clock signal is still turned on and consumes power continuously. The power thus consumed is a waste of energy. With the rapid advance in technologies, the clock signal is going to operate at a higher frequency so that the power consumed by the clock signal is correspondingly greater and the problem of power wastage becomes more seriously.
Accordingly, the inventor proposes a power-saving control circuit and method suitable for circuits including a FIFO register to revolve the foregoing problem.